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lt3694/lt3694-1 1 36941fb typical application description 36v, 2.6a monolithic buck regulator with dual ldo the lt ? 3694/lt3694-1 are monolithic, current mode dc/dc converters with dual, low dropout regulator con- trollers. the switching converter is a step-down converter capable of generating up to 2.6a at its output. each regu - lator has independent track/soft-start circuits simplifying power supply sequencing and interfacing with micro- controllers and dsps.the switching frequency is set with a single resistor with a range of 250khz to 2.5mhz. the high switching frequency permits the use of small inductors and ceramic capacitors leading to very small triple output solutions. the constant- switching frequency, combined with low impedance ce - ramic capacitors, results in low, predictable output ripple. protection circuitry senses the current in the power switch and external schottky catch diode to protect the lt3694 against short-circuit conditions. frequency foldback and thermal shutdown provide additional protection. with its wide input voltage range of 4v to 36v, the lt3694 regulates a broad array of power sources from 4-cell batteries and 5v logic rails to unregulated wall transformers, lead acid batteries and distributed power supplies. the lt3694 can be synchronized to an external clock with the sync pin while the lt3694-1 offers a clkout pin allowing other dc/dc converters to synchronize to the lt3694-1 clock. features applications n wide input range: 4v to 36v n overvoltage shutdown protects circuit through 70v transients n 2.6a output switching regulator with internal power switch n dual, low dropout, linear regulator controllers with programmable current limit n tracking/soft-start inputs and power good output simplify soft-start and supply sequencing n uses small inductors and ceramic capacitors n v out(min) = 0.75v (buck and ldos) n adjustable 250khz to 2.5mhz switching frequency n accurate enable threshold allows user programmable undervoltage lockout n options for clock synchronization (lt3694) or clock output to enable synchronization to other switching regulators (lt3694-1) n thermally enhanced 28-lead 4mm 5mm qfn and 20-lead tssop packages n automotive n industrial n dsl and cable modems n distributed power regulation n wall transformer regulation sw fb3 pgoodrt fb2sync v in v c1 bias v in 4.5v to 36v f sw = 800khz gnd lt3694 36941 ta01a trk/ss1trk/ss2 trk/ss3 lim2 drv2 da fb1 lim3 drv3 en/uvlo bst out13.3v 1.7a out31.8v 450ma out2 2.5v 450ma 47f 34k b340a 4.7h 0.22f 10k out1 out1 41.2k 15.4k 24.9k 10.7k 51.1k 11k 2.2f 4.7f 2.2f 1nf 0.1 0.1 330pf efficiency at v out = 3.3v l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 90 80 70 60 50 100 i out (a) efficiency (%) 0 1 2 3 36941 ta01b v in = 4.5v v in = 12v v in = 36v f sw = 800khz downloaded from: http:///
lt3694/lt3694-1 2 36941fb absolute maximum ratings v in , en/uvlo (note 6) ............................... C0.3v to 70v bst ........................................................................... 55v bst above sw .......................................................... 25v pgood ...................................................................... 16v trk/ss, v c , fb, rt, sync pins ................................... 6v bias, lim2, lim3 pins ............................................... 7v (note 1) order information lead free finish tape and reel part marking* package description temperature range lt3694eufd#pbf lt3694eufd#trpbf 3694 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3694iufd#pbf lt3694iufd#trpbf 3694 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3694efe#pbf lt3694efe#trpbf lt3694fe 20-lead plastic tssop C40c to 125c lt3694ife#pbf lt3694ife#trpbf lt3694fe 20-lead plastic tssop C40c to 125c lt3694-1eufd#pbf lt3694-1eufd#trpbf 36941 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3694-1iufd#pbf lt3694-1iufd#trpbf 36941 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3694-1efe#pbf lt3694-1efe#trpbf lt3694fe-1 20-lead plastic tssop C40c to 125c lt3694-1ife#pbf lt3694-1ife#trpbf lt3694fe-1 20-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 29 gnd 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 en/uvlo sync (clkout) pgood rt trk/ss1trk/ss2 fb2 drv2 dabst bias v c1 fb1trk/ss3 fb3 drv3 v in v in gndgnd sw sw lim2 gndgnd gnd gnd lim3 7 17 18 19 20 21 2216 8 15 ja = 34c/w exposed pad (pin 29) is gnd, must be soldered to pcb lt3694-1 pinout is shown in parenthesis fe package 20-lead plastic tssop 12 3 4 5 6 7 8 9 10 top view 2019 18 17 16 15 14 13 12 11 v in en/uvlo sync(clkout) pgood rt trk/ss1trk/ss2 fb2 drv2 lim2 swda bst bias v c1 fb1trk/ss3 fb3 drv3 lim3 21 gnd ja = 38c/w exposed pad (pin 21) is gnd, must be soldered to pcb lt3694-1 pinout is shown in parenthesis pin configuration operating junction temperature range (notes 2 and 5) lt3694e ............................................. C40c to 125c lt3694i .............................................. C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) (tssop only) ................................................... 300c downloaded from: http:///
lt3694/lt3694-1 3 36941fb electrical characteristics parameter conditions min typ max units v in internal undervoltage lockout l 3.5 3.8 4 v overvoltage shutdown threshold l 36 38 40 v input quiescent current not switching 1 2 ma bias quiescent current not switching 2 3.5 ma shutdown current v en/uvlo = 0.1v 0.1 2 a en/uvlo threshold, bias on 350 500 mv en/uvlo threshold, switching on l 1.16 1.2 1.23 v reference voltage line regulation 5v < v in < 36v 0.01 %/v switching frequency r t = 40.2k l 0.9 1.0 1.1 mhz sync input frequency range lt3694 only l 0.25 2.5 mhz v ih , sync lt3694 only l 1.5 v v il , sync lt3694 only l 0.35 v v oh , clkout i clkout = C50a, lt3694-1 only l 1.6 2.6 v v ol , clkout i clkout = 50a, lt3694-1 only l 0.3 v pgood output voltage low i pgood = 250a 0.2 0.4 v pgood leakage v pgood = 2v 10 1000 na pgood threshold (relative to v fb ) (note 8) 86 90 94 % switching regulator feedback pin voltage l 735 750 765 mv feedback pin bias current l C50 C500 na error amplifier transconductance 350 s error amplifier voltage gain 600 v/v trk/ss pull-up current C2 C3 C4 a trk/ss threshold to start switching 35 50 70 mv v c1 source current v c = 0.6v C20 a v c1 sink current v c = 0.6v 28 a v c1 clamp voltage 2 v v c1 switching threshold 0.75 v v c1 to switch current gain 3.6 a/v switch leakage current v in = 36v 0.01 10 a minimum boost voltage above switch (note 4) 1.8 2.5 v switch current limit (note 3) (note 3) 10% duty cycle l 3.5 4.9 6 a switch v cesat i sw1 = 3a 600 mv bst operating current i sw1 = 3a 60 ma v f , bst diode i bst = 100ma 0.8 v i l bst diode v bst C v bias = 36v 1 a da current limit l 2.6 3.6 4.5 a minimum switch off-time l 140 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, v bias = 3v, unless otherwise noted. (notes 2, 9) downloaded from: http:///
lt3694/lt3694-1 4 36941fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, v bias = 3v, unless otherwise noted. (notes 2, 9) parameter conditions min typ max units ldo regulator feedback pin voltage l 735 750 765 mv feedback pin bias current l C50 C500 na error amplifier voltage gain 2800 trk/ss pull-up current C2 C3 C4 a trk/ss threshold to shut down ldo 35 50 70 mv line regulation 5v < v in < 36v 0.025 %/v load regulation i drv from 0.1ma to 10ma 0.5 mv/ma base drive l 10 15 20 ma current limit threshold l 47 60 70 mv short-circuit current limit threshold v fb = 0 22 26 30 mv minimum bias to drv voltage (note 7) i drv = 10ma l 0.3 0.9 v minimum v in to drv voltage i drv = 10ma l 2.0 2.3 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3694e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3694i is guaranteed to meet performance specifications from C40c to 125c junction temperature. note 3: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles.note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating range when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: absolute maximum voltage at v in and en/uvlo pins is 70v for non-repetitive, 1 second transients and 36v for continuous operation.note 7: the ldo will function if the bias to drv differential is not met, but the base drive current will be drawn from v in instead of bias. note 8: the pgood pin will pull low when the voltage on any of the three fb pins is lower than the pgood threshold value.note 9: positive currents flow into pins, negative currents flow out of pins. minimum and maximum values refer to absolute values. downloaded from: http:///
lt3694/lt3694-1 5 36941fb temperature (c) C50 C5 normalized frequency shift (%) C3 C1 1 0 50 100 3 5 C4 C2 0 2 4 150 36941 g09 r t = 200k r t = 40.2k r t = 10.7k switch current (a) 0 0 boost pin current (ma) 20 40 60 1 2 10 30 50 70 3 36941 g03 temperature (c) C50 3.0 switch i lim (a) 3.5 4.5 0 50 100 5.04.0 150 36941 g04 temperature (c) C50 0 time (ns) 40 80 120 0 50 100 160 20 60 100 140 150 36941 g06 i sw = 1a minimumon-time minimumoff-time temperature (c) C50 740 v fb (mv) 748 756 0 50 100 760 744 752 746 754 758 742 750 150 36941 g07 r t (k) 0 50 100 2.0 frequency (mhz) 2.5 150 200 1.5 1.00.5 0 3.0 36941 g08 switch current (a) 0 switch v cesat (v) 0.4 0.5 0.3 0.2 2 1 3 0.1 0 0.6 36941 g02 0.80.7 typical performance characteristics switch current limit vs temperature switch minimum on-time and off-time vs temperature v fb vs temperature frequency vs r t frequency shift vs temperature bst pin current vs switch current efficiency at v out = 5v switch v cesat vs switch current switch current limit vs duty cycle v in = 12v, t a = 25c, unless otherwise noted. 0 60 100 40 20 80 switch duty cycle (%) switch i lim (a) 4.5 4.0 3.5 3.0 5.0 36941 g05 C45c 150c 25c i out (a) 0 efficiency (%) 90 80 70 2 1 3 60 50 100 36941 g01 v in = 6.3v v in = 12v v in = 36v f sw = 800khz downloaded from: http:///
lt3694/lt3694-1 6 36941fb temperature (c) C50 0 en/uvlo threshold (v) 0.4 0.8 1.2 0 50 100 1.4 0.2 0.6 1.0 150 36941 g11 uvlo switching threshold bias currentshutdown threshold temperature (c) C50 C5 normalized current limit (%) C3 2 0 50 100 5 C1C4 C2 41 30 150 36941 g13 drv current (ma) 0 v in to drv voltage (v) 2.0 2.5 1.5 1.0 6 10 4 2 8 0.5 0 36941 g15 0 6 10 4 2 8 drv current (ma) bias to drv voltage (v) 0.3 0.4 0.2 0.1 0 0.5 36941 g16 v in = 5v v bias = 4.4v typical performance characteristics ldo current limit vs v fb (foldback) ldo minimum v in to drv voltage vs drv current ldo minimum bias to drv voltage vs drv current 10hz to 100khz ldo output noise en/uvlo thresholds vs temperature minimum input voltage vs load current (v in to start) ldo current limit vs temperature v in = 12v, t a = 25c, unless otherwise noted. temperature (c) C50 2.0 trk/ss current (a) 2.5 3.5 0 50 100 4.03.0 150 36941 g10 i trk/ss vs temperature feedback voltage (v) 0 current limit voltage (mv) 40 50 30 20 0.4 0.2 0.6 0.8 10 0 60 36941 g14 C40c +150 c load current (a) 0.001 6.0 input voltage (v) 6.5 0.01 0.1 1 5.5 5.04.5 4.0 7.0 36941 g12 v out = 5v f sw = 800khz to run to start 1ms/div 10mv/div 36941 g17 v out = 2.5v i out = 0.25a zxtcm322 pass xstr downloaded from: http:///
lt3694/lt3694-1 7 36941fb pin functions v in (pin 1/pins 27, 28): the v in pin supplies power to the internal switch of the 2.6a regulator and to the lt3694s internal reference and start-up circuitry. this pin must be locally bypassed. en/uvlo (pin 2/pin 1): the en/uvlo pin is used to shut down the lt3694. it can be driven from a logic level or used as an undervoltage lockout by connecting a resistor divider from v in . clkout (pin 3/pin 2): digital clock output. the clkout pin allows synchronization of other switching regulators (lt3694-1 only). sync (pin 3/pin 2): frequency synchronization input. connect a frequency source to this input if synchronization is desired. connect sync to ground if not used (lt3694 only). pgood (pin 4/pin 3): open collector output. pgood is pulled low when any of the three regulators drops out of regulation (v fb < 90% of nominal value). rt (pin 5/pin 4): the rt pin requires a resistor to ground to set the operating frequency of the lt3694. if synchroniz - ing the lt3694 to an external clock, the resistor should be set to program the frequency at least 20% below the synchronization frequency. trk/ss1, trk/ss2 , trk/ss3 (pins 6, 7, 14/pins 5, 6, 17): the trk/ss pins allow a regulator to track the output of another regulator. when the trk/ss pin is below 0.75v, the fb pin regulates to the trk/ss voltage. this pin can also be used as a soft-start by connecting a capacitor from trk/ss to ground. the trk/ss pins should be left open if neither feature is used. fb1, fb2, fb3 (pins 15, 8, 13/pins 18, 7, 16): negative inputs of the error amplifiers. the lt3694 regulates each feedback pin to the lesser of 0.75v or the corresponding trk/ss pin voltage. connect the feedback resistor divider taps to these pins. drv2, drv3 (pins 9, 12/pins 8, 15): the drv pins provide the base drive for the external npn transistors for the ldo regulators. the drv pins can provide up to 6v of base drive. lim2, lim3 (pins 10, 11/pins 9, 14): the lim pins provide current limiting on the ldo pass transistors by sensing a voltage on an external sense resistor connected to the bias pin. these pins should be connected to bias if this function is not used. gnd (pins 10, 11, 12, 13, 25, 26) ufd package only: power and signal ground. v c1 (pin 16/pin 19): output of the internal error amp. the voltage on this pin controls the peak switch cur- rent. this pin is normally used to compensate the control loop. the switching regulator can be shut down by pulling the v c1 pin to ground with an nmos or npn transistor. bias (pin 17/pin 20): the bias pin supplies the current to the lt3694s internal regulator and boost circuits. this must be connected to a voltage source above 3v, usually to v out1 . the ldo pass transistor base current will also come from the bias pin if it is at least 1.8v above the ldo output. bst (pin 18/pin 21): the bst pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. da (pin 19/pin 22): the da pin senses the catch diode current to prevent excessive inductor current in output overload or short-circuit conditions. sw (pin 20/pins 23, 24): output of the internal power switch. connect this pin to the inductor and switching diode. exposed pad (pin 21/pin 29): ground. the underside exposed pad metal of the package provides both electrical contact to ground and a conductive thermal path to the printed circuit board. the exposed pad must be soldered to a grounded pad on the circuit board for proper operation. (fe/ufd) downloaded from: http:///
lt3694/lt3694-1 8 36941fb block diagram v c1 gnd out2 fb2 0.75v 0.68v 0.9v 0.68v 0.75v 3a trk/ss1 r2 r1 fb1 da sw bst fb3 0.75v 0.68v trk/ss3 drv3 lim3 60mv pgood pg1 clk bias 2v pg1 clk 60mv 1.2v 0.5v ldo ldo trk/ss2 drv2 3a lim2 en/uvlo bias out1 out1 r c r lim2 r lim3 c c c f 36941 f01 C + C + C ++ +C C + C ++ +C +C +C thermal shutdown overvoltage shutdown master osc int reg and ref +C slope comp C + rs o C + C + C ++ rt sync (lt3694) clkout (lt3694-1) sd sd i limit clamp 3a v in v in c in c3 l1 c1 out1 out3 out1 d1 v in buck error amp figure 1. lt3694 block diagram with typical external components downloaded from: http:///
lt3694/lt3694-1 9 36941fb operation unless specifically noted, this data sheet refers to both the lt3694 and the lt3694-1 generically as the lt3694. the lt3694 is a constant-frequency, current mode, buck regulator with an internal power switch plus two low dropout linear regulator controllers. the three regulators share common circuitry including input source, voltage reference, undervoltage lockout, and enable, but are oth - erwise independent. operation can be best understood by referring to the block diagram (figure 1). if the en/uvlo pin is below 0.35v (min), the lt3694 is shut down and draws <2a from the input source tied to v in1 . if the en/uvlo pin is driven above 0.5v (typ), the internal bias circuits turn on, including the internal regulator, reference and master oscillator. the switching regulator will only begin to operate when the en/uvlo pin reaches >1.20v (typ). the en/uvlo pin can be driven from a logic gate or can be used as an undervoltage lockout by using a resistor divider to v in . the switcher is a current mode regulator. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, current mode control improves loop dynamics and provides cycle-by- cycle current limit. a pulse from the oscillator sets the rs flip-flop and turns on the internal npn bipolar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c1 , the current comparator resets the rs flip-flop, turning off the switch. the current in the inductor flows through the external, schottky, catch diode, and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way, the voltage on the v c1 pin controls the current through the inductor to the output. the internal error amplifier regulates the output voltage by continually adjusting the v c1 pin voltage. the threshold for switching on the v c1 pin is 0.75v and an active clamp of 2v limits the output current. overcurrent protection is provided by the da comparator. the da comparator senses the catch diode current and will delay the switch-on cycle if the diode current is too high at the beginning of a cycle. t he trk/ss pins override the 0.75v reference for the fb pins when the trk/ss pins are below 0.75v. this allows either coincident or ratiometric supply tracking on start-up as well as a soft-start capability. the switch driver operates either from v in or from the bst pin. an external capacitor is used to generate a voltage at the bst pin that is higher than the input supply. this al - lows the driver to saturate the internal bipolar npn power switch for efficient operation. the bias pin allows the internal circuitry to draw its cur - rent from a voltage supply lower than v in , reducing power dissipation and increasing efficiency. if the voltage on the bias pin falls below 2.7v, then its quiescent current will flow from v in . the ldo regulator uses an external npn pass transistor to form a linear regulator. the loop is internally compensated to be stable with a minimum load capacitance of 2.2 f. the ldo also has a foldback current limiter available to protect the external transistor under overload conditions the overvoltage detection shuts down the lt3694 if the input voltage goes above 38v. this will prevent the switch from turning on under high voltage conditions and allows the lt3694 to survive transient input voltages up to 70v. downloaded from: http:///
lt3694/lt3694-1 10 36941fb step down switching regulator feedback resistor network the output voltage is programmed with a resistor divider (refer to the block diagram in figure 1) between the output and the fb pin. choose the resistors according to: r1 = r2 v out 750mv ? 1 ?? ? ?? ? the parallel combination of r1 and r2 should be 10k or less to avoid bias current errors. input overvoltage lockout an important feature of the lt3694 is the ability to survive transient surges on the input voltage of up to 70v. this is accomplished by shutting off the regulators to keep this high voltage off the critical components. the overvoltage lockout trips when the input voltage exceeds 38v. input voltage range the minimum operating voltage is determined either by the lt3694s internal undervoltage lockout or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltage: dc = v out + v f v in ? v sw + v f where v f is the forward voltage drop of the catch diode and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of: v in(mincf) = v out + v f dc max(cf) ? v f + v sw the duty cycle is the fraction of time that the internal switch is on during a clock cycle. the maximum duty cycle for constant-frequency operation given by dc max(cf) = 1 C t off(min) ? f sw . however, unlike most fixed frequency regulators, the lt3694 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (c3 in figure 1) to fully saturate the output switch. a forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capaci - tor needs to be recharged. this operation has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. the resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: dc max = b b + 1 where b is the output current divided by the typical boost current from the bst pin current vs switch cur - rent curve in the typical performance characteristics section. the maximum voltage, v in , for constant-frequency opera - tion is determined by the minimum duty cycle dc min : v in(maxcf) = v out + v f dc min ? v f + v sw with dc min = t on(min) ? f sw thus, both the maximum and minimum input voltages for constant-frequency operation are a function of the switching frequency and output voltage. therefore, the maximum switching frequency must be set to a value that accommodates the input and output voltage parameters and must meet both of the following criteria: f max1 = v out + v f v in(maxcf) ? v sw + v f ?? ? ?? ? ? 1 t on(min) f max2 = 1 ? v out + v f v in(mincf) ? v sw + v f ?? ? ?? ? ? 1 t off(min) the values of t on(min) and t off(min) are functions of i sw and temperature (see chart in the typical perform- ance characteristics section). worst-case values for switch currents greater than 0.5a are t on(min) = 130ns and applications information downloaded from: http:///
lt3694/lt3694-1 11 36941fb applications information t off(min) = 140ns. f max1 is the frequency at which the mini - mum duty cycle is exceeded. the regulator will skip on pulses in order to reduce the overall duty cycle at frequencies above f max1 . it will continue to regulate but with increased inductor current and greatly increased output ripple. the increased peak inductor current in pulse-skipping will also stress the switch transistor at high voltages and high switching frequency. f max2 is the frequency at which the maximum duty cycle is exceeded. if there is sufficient charge on the bst capacitor, the regulator will skip off periods to increase the overall duty cycle at frequencies above f max2 . it will continue to regulate but will not have constant-frequency operation.note that the restriction on the operating input voltage refers to steady-state limits to keep the output in regulation in constant-frequency mode; the circuit will tolerate input voltage transients up to the absolute maximum rating. switching frequency once the upper limit for the switching frequency is found from the duty cycle requirements, the frequency may be chosen below the upper limit. lower frequencies result in lower switching losses, but require larger inductors and capacitors. the user must decide the best trade-off. the switching frequency is set by a resistor connected from the rt pin to ground, or by forcing a clock signal into the sync pin (lt3694 only). the lt3694 applies a voltage of 0.75v across this resistor and uses the current to set the oscillator speed. the switching frequency is given by the following formula: f sw = 49.8 r t + 8.8 where f sw is in mhz and r t is in k. the formula is accurate within 2% over the frequency range. table 1 shows the typical measured value of r t for several com - mon switching frequencies. table 1: r t for common frequencies switching frequency (mhz) r t (k) 0.25 193 0.5 90.2 0.75 56.6 1 40.2 1.25 30.5 1.5 23.8 1.75 19.6 2 16.0 2.25 13.5 2.5 11.4 for external clocks applied to the sync pin (lt3694 only), the circuit will support v h logic levels from 1.8v to 5v cmos or ttl. the duty cycle needs a minimum on time of 100ns and a minimum off time of 100ns. when operating in sync mode, r t should be set to provide a frequency at least 20% below the minimum sync frequency. inductor selection and maximum output current a good first choice for the inductor value is: l = v out + v f 1.25a ? f where f is the switching frequency in mhz, l is the inductor value in h, v out is the output voltage and v f is the catch diode voltage drop. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the lt3694 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3694 will deliver depends on the switch current limit, the inductor value and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: ? i l = (1 ? dc) v out + v f l ? f downloaded from: http:///
lt3694/lt3694-1 12 36941fb applications information where f is the switching frequency of the lt3694 and l is the value of the inductor. the peak inductor and switch current is: i swpk = i lpk = i out + ? i l 2 to maintain output regulation, this peak current must be less than the lt3694s switch current limit, i lim . i lim is at least 3.5a at low duty cycles (0.1) and decreases linearly to 2.8a at dc = 0.8. the minimum inductance can now be calculated as: l min = 1 ? dc min 2 ? f ? v out + v f i lim ? i out however, its generally better to use an inductor larger t han the minimum value. the minimum inductor has large ripple currents which increase core losses and require large output capacitors to keep output voltage ripple low. select an inductor greater than l min that keeps the ripple current below 30% of i lim . for input voltages greater than 30v, use an inductor with a saturation current of 6a or greater and an inductance value of 3.3h or greater. the inductors rms current rating must be greater than the maximum load current and its saturation current should be greater than i lpk . for highest efficiency, the series resistance (dcr) should be less than 0.1. table 2 lists several vendors and types that are suitable. table 2. inductors series inductance range (h) current range (a) manufacturer we-hc 1 to 6.5 6 to 15 wrth elektronik www.we-online.com mss1048 0.8 to 8 4 to 8 coilcraft www.coilcraft.com cdrh103r 0.8 to 10 2.8 to 8.3 sumida www.sumida.com vlf 2.2 to 10 3.8 to 7.7 tdk www.component.tdk. com ihlp-2525cz-11 1 to 10 2.5 to 9.5 vishay www.vishay.com this analysis is valid for continuous mode operation (i out > i lim /2). for details of maximum output current in discontinuous mode operation, see the linear technol - ogy application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. this minimum inductance is: l min = (v out + v f ) 2a ? f sw with l min in h and f sw in mhz. a detailed discussion of subharmonic oscillations can be found in the linear technology application note 19. input capacitor selection bypass the input of the lt3694 circuit with a ceramic capacitor of x7r or x5r type. y5v types have poor performance over temperature and applied voltage, and should not be used. a 4.7f to 22f ceramic capacitor is adequate to bypass the lt3694 and will easily handle the ripple current. use a 22f capacitor with f sw between 250khz and 800khz. use a 10f capacitor with f sw be - tween 800khz and 1.6mhz. use a 4.7f capacitor above 1.6mhz. always check for sufficient margin by reducing the capacitor value until the dropout increases by >500mv. if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a lower performance electrolytic capacitor. step-down regulators draw current from the input sup - ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3694 and to force this very high frequency switching current into a tight local loop, minimizing emi. a 10f capacitor is capable of this task, but only if it is placed close to the lt3694 and the catch diode (see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3694. a ceramic input capacitor combined with trace or cable inductance forms a high downloaded from: http:///
lt3694/lt3694-1 13 36941fb quality (under damped) tank circuit. if the lt3694 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt3694s maximum input voltage rating. see linear technology application note 88 for more details. output capacitor selection the output capacitor filters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and stabilize the lt3694s control loop. because the lt3694 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. output ripple can be estimated with the following equations: v ripple = ? i l 8 ? f ? c out ; ceramic v ripple = ? i l ? esr ; electrolytic where i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = ? i l 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? i lim v out ?? ? ?? ? 2 the low esr and small size of ceramic capacitors make them the preferred type for lt3694 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types instead.electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. surge rated tantalum capacitors or low esr, organic, electrolytic capacitors intended for power supply use are suitable. choose a capacitor with a sufficiently low esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one benefit is that the larger capacitance may give better transient response for large changes in load current. table 3 lists several capacitor vendors. table 3. low esr surface mount capacitors series type manufacturer ceramic taiyo yuden www.t-yuden.com tpm, tps ceramic, tantalum avx www.avx.com t494, t495, t510, t520, t525, t530, a700 ceramic, tantalum, tantalum organic polymer, aluminum organic polymer kemet www.kemet.com poscap, os-con tantalum organic polymer, aluminum organic polymer sanyo www.sanyo.com sp-cap ceramic, aluminum organic polymer panasonic www.panasonic.com ceramic tdk www.tdk.com applications information downloaded from: http:///
lt3694/lt3694-1 14 36941fb diode selectionthe catch diode (d1 from figure 1) conducts current only during switch off time. average forward current in normal operation can be calculated from: i d(avg) = i out ? v in ? v out v in consider a diode with a larger current rating than i d(avg) when the part must survive a shorted output. the da pin monitors the current in the diode and prevents the switch from turning on at the beginning of a charge cycle if the diode current is above the da limit. therefore, under overload conditions, the average diode current will in - crease to the average of the switch current limit and the da current limit. peak reverse voltage is equal to the regulator input voltage, so use a diode with a reverse voltage rating greater than the maximum input voltage. the internal ovlo can protect the diode from excessive reverse voltage by shutting down the regulator if the input voltage exceeds 38v. table 4 lists several schottky diodes and their manufacturers. table 4. schottky diodes (40v, 3a) part number v f at 3a (v) outline manufacturer mbrs340 mbrd340 0.5 0.6 smc d-pak on semiconductor www.onsemi.com b340 smb340 0.5 0.5 smc powermite 3 diodes, inc. www.diodes.com cmsh3-40 cshd3-40 0.5 0.65 smc d-pak central semiconductor www.centralsemi.com frequency compensation the lt3694 uses current mode control to regulate the output. this simplifies loop compensation. in particular, the lt3694 does not require the esr of the output capacitor for stability, so the user is free to employ ceramic capacitors to achieve low output ripple and small circuit size. frequency compensation is provided by the components tied to the v c pin, as shown in figure 2. generally a capacitor (c c ) and a resistor (r c ) in series to ground are used. in addi - tion, there may be lower value capacitor in parallel. this capacitor (c f ) is not part of the loop compensation but is used to filter noise at the switching frequency, and is required only if a phase-lead capacitor (c pl ) is used or if the output capacitor (c1) has high esr. applications information C + 0.75v sw v c g m = 350s gnd 3m lt3694 36941 f02 r1 output esr c f c c r c error amplifier fb r2 c1 c1 current mode power stage g m = 7.5s + polymer or tantalum ceramic c pl figure 2. model for loop response loop compensation determines the stability and transient performance. the best values for the compensation net - work depend on the application and in particular the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. figure 2 shows an equivalent circuit for the lt3694 control loop. the error amplifier is a transconductance amplifier with finite output impedance. downloaded from: http:///
lt3694/lt3694-1 15 36941fb the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the v c1 pin. note that the output capacitor integrates this current, and that the capacitor on the v c1 pin (c c ) integrates the error amplifier output current, resulting in two poles in the loop. in most cases a zero is required and comes from either the output capacitor esr or from a resistor r c in series with c c . this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. a phase lead capaci - tor (c pl ) across the feedback divider may improve the transient response.figure 3 shows the transient response when the load current steps from 1a to 2.6a and back to 1a. bst and bias pin considerations capacitor c3 and the internal boost schottky diode (see t he block diagram in figure 1) are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.22f capacitor will work well. figure 4 shows three ways to arrange the boost circuit. the bst pin must be more than 2.3v above the sw pin for best efficiency. for outputs of 3v and above, the standard circuit (figure 4a) is best. for outputs between 2.8v and 3v, use a 1f boost applications information figure 3. transient load response of the lt3694 front page application as the load current is stepped from 1a to 2.6a. v out = 3.3v v in bst sw bias v in v out 4.7f c3 gnd lt3694 v in bst sw bias v in v out 4.7f c3 d2 gnd lt3694 v in bst sw bias v in v out 4.7f c3 gnd lt3694 36941 fo4 (4a) for v out > 2.8v (4b) for 2.5v < v out < 2.8v (4c) for v out < 2.5v; v in(max) = 7v figure 4. three circuits for generating the boost voltage 36941 f03 i l 1a/div v out 100mv/div 100s/div capacitor. a 2.5v output presents a special case because it is marginally adequate to support the boosted drive stage while using the internal boost diode. for reliable bst pin operation with 2.5v outputs, use a good external schottky diode (such as the on semi mbr0540), and a 1f boost capacitor (see figure 4b). for lower output voltages, the bias pin can be tied to the input (figure 4c), or to ano ther supply greater than 2.8v. tying bias to v in reduces the maximum input voltage to 7v. the circuit in figure 4a is more efficient because the bst pin current and bias pin quiescent current comes from a lower voltage source. one must also ensure that the maximum voltage ratings of the bst and bias pins are not exceeded. the minimum downloaded from: http:///
lt3694/lt3694-1 16 36941fb operating voltage of an lt3694 application is limited by the minimum input voltage (4v) and by the maximum duty cycle as outlined in a previous section. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3694 is turned on with its en/uvlo or trk/ss pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is cha rged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. figure 5 shows a plot of input voltage to start and to run as a function of load current. in many cases the discharged output capacitor will present a load to the switcher, which will allow it to start. the plots show the worst-case situation in which v in is ramping very slowly. for lower start-up voltage, the boost diode can be tied to v in , however, this restricts the input range to one-half of the absolute maximum rating of the bst pin. at light loads, the inductor current becomes discontinu - ous and the effective duty cycle can be very high. this reduces the minimum input voltage to approximately 300mv above v out . at higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle of the lt3694, requiring a higher input voltage to maintain regulation. internal undervoltage lockout the lt3694 features an internal undervoltage lockout that will shut off all three regulators if the input voltage drops too low to maintain regulation of the internal circuitry. this lockout trips when v in drops below 3.8v (typ). enable and programmable undervoltage lockout the en/uvlo pin provides both logic enable and pro - grammable undervoltage lockout functions. there are two thresholds on the en/uvlo pin. the first threshold is at 500mv (typ). when en/uvlo is below this threshold, the lt3694 is in complete shutdown and the quiescent current drops below 2a. applications information figure 5. the minimum input voltage depends on output voltage, load current and boost circuit 36941 f05 load current (a) 0.001 input voltage (v) 3.8 4.0 4.2 1 3.63.4 3.0 0.01 0.1 3.2 5.04.4 4.6 4.8 to start to run v out = 3.3v f sw = 800khz load current (a) 0.001 6.0 input voltage (v) 6.5 0.01 0.1 1 5.5 5.04.5 4.0 7.0 v out = 5v f sw = 800khz to run to start downloaded from: http:///
lt3694/lt3694-1 17 36941fb once en/uvlo climbs above the first threshold, the inter - nal circuitry of the lt3694 is turned on but the switching regulator and ldos remain shut off. a 2a current sink on the en/uvlo pin is activated to provide hysteresis for the programmable undervoltage function. the second threshold is an accurate 1.2v derived from the internal reference. when en/uvlo is above the second threshold, the regulators turn on and the 2a current sink turns off. this allows an accurate programmable uvlo function by placing a resistor divider between v in , en/uvlo and ground. figure 6a shows the en/uvlo block diagram and figure 6b shows connections for the programmable uvlo function. the trip level is set by the resistor ratio: v in(uvtrip) = 1.2v r1 + r2 r2 ?? ? ?? ? the hysteresis is set by r1: v in(uvhys) = 2a ? r1 the en/uvlo pin may be driven with a logic output if the programmable uvlo is not needed. the requirements for the logic output are a low output voltage less than 0.35v (to insure low current shutdown) and a high output volt - age greater than 1.25v. low dropout regulator each low dropout regulator comprises an error amp, loop compensation and a base drive amp. it uses the same 0.75v reference as the switching regulators. it requires an external npn pass transistor and 2.2f of output ca - pacitance for stability. the dropout characteristics will be determined by the pass transistor. the collector-emitter saturation characteristics will limit the dropout voltage. table 5 lists some suitable npn transistors with their saturation specifications. applications information figure 6. programmable uvlo application (6a) en/uvlo block diagram (6b) programmable uvlo application en/uvlo internal circuitry shutdown regulators 0.5v1.2v 2a C + C + v in v in uvlo hysteresis 2a ? r1 undervoltage trip level r1r2 en/uvlo 1.2v ? (r1 + r2) r2 lt3694 36941 fo4 the base drive voltage has a maximum voltage of 6v. this will limit the maximum output of the regulator to 6v C v be(sat) where v be(sat) is the base-emitter saturation voltage of the pass transistor. table 5. low v cesat transistors part number v cesat at i c = 1a outline manufacturer zxtn25012ez zxtn25020dg 0.06 0.075 sot-89 sot-223 zetex www.diodes.com nss20201jt1g nss12201lt1g 0.22 0.08 sc-89 sot-23 on semiconductor www.onsemi.com ctlt3410-m621 0.28 1mm 2mm tlm621 central semiconductor www.central-semi.com downloaded from: http:///
lt3694/lt3694-1 18 36941fb the ldo may be shut down if it is unused by pulling the fb pin up with a resistor that will source at least 30a. the fb pin will clamp at about 1.25v and the ldo will shut off reducing power consumption. this pull-up can be sourced from one of the lt3694 outputs provided that channel is always on when the other channels are on. the output stage of the ldo will drive the npn base from the bias voltage if it is at least 1.8v above the ldo drive voltage, otherwise the npn base current comes from v in . the base drive current is limited to 15ma.ldo fb resistor network the output voltage of the ldo regulator is programmed with a resistor divider (refer to the block diagram in figure 7) between the emitter of the external npn pass resistor and the feedback pin, fb2 or fb3. choose the resistors according to: r1 = r2 v out 0.75 ? 1 ?? ? ?? ? the parallel combination of r1 and r2 should be 10k or less to avoid bias current errors. applications information ldo current limitthe ldo has a current limit available to reduce the power consumption of the npn transistor under overload condi - tions. the current limit requires the npn transistor collector to be connected to the bias pin through a low resistance sense resistor. the current limit circuit senses the voltage drop across this resistor and reduces the base drive cur - rent when the limit voltage exceeds 60mv. this will limit the output current to 60mv/r sense . if the overload causes the output voltage to drop, the limit voltage is folded back to reduce power in the npn transis - tor. the limit circuit monitors the fb voltage and ramps the limit voltage down once v fb drops to 0.6v. the limit voltage will fold back to 26mv when v fb has dropped to 0v. the current foldback is disabled until the associated trk/ss pin rises above 0.68v. this insures proper start-up under full load conditions. figure 7 shows the ldo circuit with current limit. properly routing the current limit sense resistors is critical to minimize errors in the current limit. the sense con - nections are the bias pin (both channels) on the high side and lim2 or lim3 on the bottom side. these sense leads must be routed separately from all current carrying traces. figure 9 shows a layout that minimizes trace re - sistance errors. the current limit sense resistors (rlim2 and rlim3) are placed close together and the bias pin trace is connected to v out1 at their junction. the bottom sides of these resistors have a separate via and trace to the lim2 and lim3 pins. the foldback can dramatically reduce the power diss ipation of the npn pass transistor under short-circuit conditions. for example, an application that has v out1 = 3.3v and v out2 = 2.5v will nominally have 0.8v across the pass transistor v ce . under short-circuit conditions, the pass transistor v ce will increase to 3.3v. without foldback the power dissipation in the pass transistor will increase by more than 4x, but with foldback the power dissipation only increases by 78%. fb2 r1 out1 out2 r2 0.75v drv2 lim2 bias 60mv lt3694 C + C + 36941 fo7 r sense figure 7. ldo with current limit downloaded from: http:///
lt3694/lt3694-1 19 36941fb if the current feeding the collector of the npn through the sense resistor comes from a supply that is not connected to bias, the current limit cannot be used and the lim pin must be connected to bias to disable the current limit. tracking and soft-start the output of the lt3694 regulates to the lowest voltage present at either the trk/ss pin or an internal 0.75v reference. a capacitor from the trk/ss pin to ground is charged by an internal 3a current source resulting in a linear output ramp from 0v to the regulated output whose duration is given by: t ramp = c trkss ? 0.75v 3a at power-up or at any shutdown event, the trk/ss pins are internally pulled to ground through 100? to insure the soft-start capacitors are discharged. the pins clamp at 1.3v. ratiometric tracking is achieved by tying the trk/ss pins tied together and connecting to a single capacitor. the charge current is multiplied by the number of trk/ss pins connected. coincident tracking is accomplished by adding an addi - tional resistor divider to the master regulator output and connecting it to the trk/ss pin of the slave regulator. the resistor divider should be equal to the slaves feedback divider. keep in mind that the ldo pass transistor v ce(sat) will limit how well the ldo output can coincidentally track the switching regulator output. the trk/ss pin has a low voltage detect that insures the regulator is shut off when trk/ss is pulled low. the threshold low voltage is nominally 50mv. this allows independent on/off control of the ldos using the trk/ss pins. the logic drive should be open collector or have series resistance because the trk/ss pins are internally pulled to ground during any shutdown event. shorted and reversed input protection if an inductor is chosen that will not saturate excessively, an lt3694 buck regulator will tolerate a shorted output. there is another situation to consider in systems where the output will be held high when the input to the lt3694 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ored with the lt3694s output. if the v in pin is allowed to float and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the lt3694s internal circuitry will pull its quiescent current through its sw pin. this is fine if the system can tolerate a few ma in this state. if the en/uvlo pin is grounded, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3694 can pull large currents from the output through the sw pin and the v in pin. the circuit in figure 8 runs only when the input voltage is presentand protects against a shorted or reversed input. applications information figure 8. diode d4 prevents a shorted input from discharging a backup battery tied to the output. it also protects the circuit from a reversed input. the lt3694 runs only when the input is present v in bst gnd fb en/uvlov c sw d4 v in lt3694 36941 f08 v out backup downloaded from: http:///
lt3694/lt3694-1 20 36941fb additional vias to reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 34c/w (ufd) or ja = 38c/w (fe20). with 100 lfpm airflow, this resistance can fall by another 25%. further increases in airflow will lead to lower thermal resistance. because of the large output current capability of the lt3694, it is possible to dissipate enough heat to raise the junc - tion temperature beyond the absolute maximum. when operating at high ambient temperatures, the maximum load current should be derated as the ambient temperature approaches t j(max) . power dissipation within the lt3694 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the catch diode loss and inductor loss. the die temperature is calculated by multiplying the lt3694 power dissipation by the thermal resistance from junction-to-ambient. keep in mind other heat sourcessuch as the catch diode, inductor and ldo pass transistors. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. pcb layoutf or proper operation and minimum emi, care must be taken during printed circuit board layout. figure 9 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents flow in the lt3694s v in , da, and sw pins, the catch diode (d1) and the input capacitor (c in ). the loop formed by these components should be as small as pos - sible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components. the sw and bst nodes should be as small as possible. finally, keep the fb and v c nodes small so that the ground traces will shield them from the sw and bst nodes. the exposed pad on the bottom of the package must be s oldered to ground so that the pad acts as a heat sink. to keep thermal resistance low, extend the top side ground plane as much as possible, and add thermal vias under and near the lt3694 to additional ground planes within the circuit board and on the bottom side. high temperature considerations the pcb must provide heat sinking to keep the lt3694 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these lay - ers will spread the heat dissipated by the lt3694. place applications information downloaded from: http:///
lt3694/lt3694-1 21 36941fb figure 9. a good pcb layout ensures proper, low emi operation thermal vias to ground plane vias to bias signal vias to inner layers vias to q2 collector 36941 f09 vias to lim2/lim3 pcb bottom side is a solid ground plane v in v out2 c out1 v out3 v out1 c in q2 d1 l1 r lim2 r lim3 q3 gnd applications information downloaded from: http:///
lt3694/lt3694-1 22 36941fb typical applications sw fb3 v in v c1 bias v in 6v to 16v transient to 70v uvlo 5.8v f sw = 2mhz gnd lt3694 36941 ta02 trk/ss1trk/ss2 trk/ss3 lim2 drv2 da fb1 lim3 drv3 en/uvlo bst out13.3v 1.7a out31.8v 450ma out2 2.5v 450ma 10f 34k b340a 1.2h 100k 26.7k 10k out1 out1 zxtn25012ez zxtn25012ez 34k 14k 24.9k 10.7k 16k 10k 2.2f 4.7f 0.1f 2.2f 1nf 0.1 0.1 100pf pgoodrt fb2sync automotive input range (6v to 16v) to 3.3v, 2.5v, 1.8v downloaded from: http:///
lt3694/lt3694-1 23 36941fb out33.3v 450ma out1 zxtn25020dg 20k 34k10k 2.2f 0.1 1000pf sw fb3 sync v in v c1 bias v in 6.3v to 36v transient to 70v enable enld02enld03 clkin f sw = 800khz gnd lt3694 36941 ta03 trk/ss1trk/ss2 trk/ss3 lim2 drv2 da fb1 lim3 drv3 en/uvlo bst out15v 1.7a 22f 57.6k b340a 5.4h 10.2k 10f 1nf 1nf 1nf out2 2.5v 450ma out1 zxtn25020dg 24.9k 10.7k 66.5k 2.2f 0.1 pgoodrt fb2sync 0.22f wide input range to (6.3v to 36v) to 5v, 3.3v, 2.5v with independent on/off control of the ldos typical applications downloaded from: http:///
lt3694/lt3694-1 24 36941fb typical applications sw fb3 fb2 sync rt v in v in v c1 bias v in 6v to 36v transient to 70v uvlo 5.8v f sw = 500khz gnd pgood lt3694 36941 ta04 trk/ss1trk/ss2 trk/ss3 lim2 drv2 da fb1 lim3 drv3 en/uvlo bst out11.8v 2.6a out32.5v out2 3.3v 47f 14k b340a out2 0.22f 3.3h 10k out2 zxtn25020dg zxtn25020dg 25.5k 26.7k 24.9k 34k 10k 90.2k 10.7k 2.2f 22f 100k 4.7nf 2.2f 470pf the ldo output current capability is limited by the power dissipation of the npn pass transistors wide input range (6v to 36v) to 1.8v, 2.5v and 3.3v downloaded from: http:///
lt3694/lt3694-1 25 36941fb package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 27 28 12 bottom viewexposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 ? 0.05 0.25 ? 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
lt3694/lt3694-1 26 36941fb package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (cb) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation cb downloaded from: http:///
lt3694/lt3694-1 27 36941fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 01/11 corrected the pin configuration drawing and package description for the tssop package. 2 b 03/12 added sync input layout frequency range, added conditions to sync and clkout i/o specs. fixed typo in exposed pad description.updated fe20 package 37 26 downloaded from: http:///
lt3694/lt3694-1 28 36941fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0312 rev b ? printed in usa related parts part number description comments lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode ? operation v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3mm 3mm dfn-10 and msop-10e packages lt3500 36v, 40v max , 2a, 2.5mhz high efficiency step-down dc/dc converter and ldo controller v in : 3.6v to 36v, v out(min) = 0.8v, i q = 2.5ma, i sd < 10a, 3mm 3mm dfn-10 package lt3507 36v, 2.5mhz, triple (2.4a + 1.5a + 1.5a (i out )) with ldo controller high efficiency step-down dc/dc converter v in : 4v to 36v, v out(min) = 0.8v, i q = 7ma, i sd < 1a, 5mm 7mm qfn-38 package lt3685 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3mm 3mm dfn-10 and msop-10e packages lt3970 40v, 350ma, 2mhz high efficiency micropower step-down dc/dc converter v in : 4v to 40v, transient to 60v, v out(min) = 1.21v, i q = 2a, i sd < 1a, 3mm 2mm dfn-10 and msop-10 packages lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in : 3.6v to 58v, transient to 80v, v out(min) = 0.8v, i q = 85a, i sd < 1a, 3mm 4mm dfn-16 and msop-16e packages typical application sw fb3 fb1 fb2 rt v in v c1 bias v in 6v to 28v transient to 70v f sw = 1mhz gnd lt3694-1 36941 ta05 trk/ss1trk/ss2 trk/ss3 lim2 drv2 da lim3 drv3 en/uvlo bst out13.3v 500ma out31.8v 200ma out2 2.5v 450ma 22f 34k b340a 2.2h 0.1f 10k out1 out1 zxtn25012ez zxtn25012ez 30.9k 14k 24.9k 10.7k 40.2k 10k 255k 20pf 10f 2.2f 200k 2.2f 20pf pgood clkout 0.2 0.1 270pf 52.3k 200k 1nf en4 en5 en6 out4 1.8v, 800ma 511k 226k 226k 1.5h 1.5h 1.5h 10f 10f 20pf 301k 10f 10f sw2 v fb1 v in pv in v fb2 v fb3 gnda gnda pgnd pgnd ltc3545 run1pgood1 run2 pgood2 run3 sync/mode sw1 sw3 out51.2v 800ma out6 1.5v, 800ma 2.2f 6v to 28v input range with cascaded step down ? 3.3v, 2.5v and 1.8v outputs plus independently enabled 1.8v, 1.5v and 1.2v outputs downloaded from: http:///

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